Hybrid laser diode suits CMOS wafer fabrication process

A Grenoble, France-based research team at CEA Leti and chip maker STMicroelectronics say that they have demonstrated the first hybrid III-V/silicon laser to be fabricated using a wafer manufacturing process suited to large-scale production.

In a paper presented at this week’s International Electron Devices Meeting (IEDM) in San Francisco, Bertrand Szelag and colleagues reported that the distributed feedback (DFB) emitter yielded a maximum output power of 4 mW, with a side-mode suppression ratio (SMSR) of 50 dB.

The work suggests that it should be possible to make lasers that produce a useful amount of power with a silicon wafer fabrication process suited to large-scale integration, and analogous to the way in which conventional silicon chips are made.

While hybrid material approaches combining the light-emitting properties of compound semiconductors and the utility of silicon have been reported previously, so far none have proved compatible with large-diameter silicon wafers and fully-scaled CMOS processes.

This latest work has the advantage of a fully planar process flow, and if it does become the first laser diode fabrication process to transfer into truly large-scale production, the development could prove hugely significant for low-cost silicon photonics integration. Applications in data centers, high-performance computing, and even quantum-secured communications could follow.

CMOS compatibility
“In this paper we present, to the best of our knowledge, the first integration of a hybrid III-V/Si DFB laser in a fully CMOS-compatible 200 mm [silicon wafer diameter] technology,” writes the team, adding:

“The novelty of our approach also relies on the use of innovative laser electrical contacts which do not contain any noble metals such as gold and for which integration ‘lift-off’ based process are prohibited. Thanks to these properties, the contacts [use] a planarized back-end, and are CMOS-compatible both in terms of composition and integration scheme.”

Detailing some early steps in the device fabrication process, the team notes the use of localized silicon thickening, to create a 500 nm-thick layer of silicon underneath the III-V material gain section.

After using deep-ultraviolet (DUV) lithography to pattern Bragg gratings into the thickened silicon waveguide region beneath the gain area, the individual silicon-on-insulator (SOI) and indium phosphide (InP) wafers hosting the critical elements of the hybrid device are bonded with oxygen plasma surface activation.

The InP substrate is then etched away, leaving the multi-quantum-well epitaxial structure that forms the active laser element on top of the 200 mm-diameter SOI wafer.

Among the remaining process steps is contact metallization, with Szelag and his co-workers electing to use nickel contacts because of their wide availability and compatibility with the active layer structure of III-V materials. Laser diodes typically use gold contacts, which are unsuitable for the “lift-off” process.

Laser output
Tested under continuous electrical pumping at room temperature, the device produced up to 4 mW output power at 1300 nm, with the 50 dB SMSR figure indicating good spectral purity.

While the output power appeared variable as the applied drive current increased, the research team says that the lasing threshold current was stable between 50 mA and 65 mA.

“The series resistances are in the range of 10 Ω, which is in line with devices fabricated with non-CMOS compatible process and materials,” they note. “These results therefore validate the integration and the choice of fully CMOS-compatible Ni-based alloys as III-V metallization.”

In conclusion the team reports that the approach, which benefits from the organization’s wider silicon photonics technology developed with partners at imec, STMicroelectronics and elsewhere as part of the EU-funded “PLAT4M” project, validates a fully CMOS-compatible scheme for hybrid laser fabrication.

“Future work will concern the implementation of optimized designs taking into account the use [of] amorphous silicon to improve the emitted power level,” they add. “Two metal levels [of] routing will also be used to improve the current driving capabilities and reduce furthermore the series resistance.”

CEA Leti and the various PLAT4M partners said previously that they had developed three different silicon photonics processes during the four-year course of the €15.3 million project, which ended earlier this year and had the goal of "making silicon photonics technology ready for transition to industry".

(From: http://optics.org/news/8/12/7)

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